1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly to a liquid crystal display device and a method of fabricating a liquid crystal display device.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device displays images by adjusting a transmittance of a liquid crystal material using an electric field. The LCD device comprises a liquid crystal display panel having liquid crystal cells arranged in a matrix configuration and a driving circuit to drive the liquid crystal display panel. In addition, pixel electrodes and a common electrode are mounted in the liquid crystal display panel in order to induce the electric field to the liquid crystal material. Each of the pixel electrodes is provided at every liquid crystal cell formed on a lower substrate, and the common electrode is formed as a single electrode across an entire surface of an upper substrate. Each of the pixel electrodes is connected to a thin film transistor (TFT), which functions as a switching device, wherein the pixel electrode and common electrode drive the liquid crystal cell in accordance with a data signal supplied through the thin film transistor.
FIG. 1 is a plan view of a lower substrate of an LCD device according to the related art, and FIG. 2 is a cross sectional view along II-II′ of FIG. 1 according to the related art. In FIGS. 1 and 2, a lower array substrate comprises a thin film transistor (TFT) T that is located at an intersection of a data line 4 and a gate line 2, a pixel electrode 22 connected to a drain electrode 10 of the TFT T, and a storage capacitor SC located at an overlapping part of the pixel electrode 22 and a pre-stage gate line 2.
The TFT T comprises a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and the drain electrode 10 connected to the pixel electrode 22 through a drain contact hole 20. In addition, the TFT T comprises semiconductor layers 14 and 16 to form a conducting channel between the source and drain electrodes 8 and 10 by using a gate signal supplied to the gate electrode 6. Accordingly, the TFT T selectively provides the pixel electrode 22 with a data signal from the data line 4 in response to a gate signal supplied to the gate line 2.
The pixel electrode 22 is located in a cell region partitioned by the data and gate lines 4 and 2 and is made of a transparent conducting material having a high light transmittance. The pixel electrode 22 is formed on a protection layer 18, which is provided on an entire surface of the lower array substrate, and is electrically connected to the drain electrode 10 through the drain contact hole 20 formed through the protection layer 18. Accordingly, the pixel electrode 22 generates a potential difference from a common transparent electrode (not shown) formed on an upper substrate by the data signal supplied through the TFT T. Liquid crystal molecules of a liquid crystal material provided between the lower substrate 1 and the upper substrate (not shown) rotate because of a dielectric anisotropy created by the potential difference. Thus, incident light transmitted through the pixel electrode 22 from a light source is transmitted to the upper substrate by the rotation of the liquid crystal molecules.
The storage capacitor SC functions to restrain a voltage fluctuation of the pixel electrode 22. The storage capacitor SC comprises an adjacent (i.e., pre-stage) gate line 2, a gate insulation film 12, and the semiconductor layers 14 and 16 provided between the pre-stage gate line 2 and a storage electrode 24 interconnect to the pixel electrode 22 via a storage contact hole 26.
FIGS. 3A to 3D are cross sectional views of a method of fabricating the lower substrate of FIG. 2 according to the related art. In FIG. 3A, the gate electrode 6 and the gate line 2 are formed on the lower array substrate 1. Then, a gate metal layer is formed on the lower array substrate 1 by a deposition method, such as a sputtering, and includes aluminium (Al) or an aluminium alloy. Next, the gate metal layer is patterned by photolithograpic and etching processes using a first mask, thereby forming the gate electrode 6 and the gate line 2 on the lower array substrate 1
In FIG. 3B, the gate insulation film 12, the first semiconductor layer (i.e., active layer) 14, the second semiconductor layer (i.e., ohmic contact layer) 16 an ohmic contact layer 16, the source electrode 8, the drain electrode 10, the storage electrode 24, and the data line 4 are formed on the lower array substrate 1 having the gate electrode 6 and gate line 2.
For example, the gate insulation film 12, the first and second semiconductor layers 14 and 16 and a data metal layer are sequentially deposited using a deposition method, such as chemical vapor deposition and sputtering, on the lower array substrate 1. The gate insulating film 12 includes silicon oxide (SiOx) or silicon nitride (SiNx), the first semiconductor layer 14 includes undoped amorphous silicon, the second semiconductor layer 16 includes impurity-doped amorphous silicon, such N-type or P-type impurities, and the data metal layer includes molybdenum (Mo) or an molybdenum alloy.
Next, a photoresist pattern is formed by photolithograpic processes using a second mask on the data metal layer. Accordingly, a diffraction mask having a diffraction part corresponding to a channel part of the TFT T is used as the second mask, whereby the photoresist pattern of the channel part has a height lower than a height of a source/drain pattern part and a storage pattern part. Then, the data metal layer is patterned by wet etching processes using the photoresist pattern to form the data line 4, the storage electrode 24, and the source and drain electrodes 8 and 10.
Next, the first and the second semiconductor layers 14 and 16 are simultaneously patterned by dry etching processes using the same photoresist pattern to form the active layer 14 and the ohmic contact layer 16. Then, the photoresist pattern is removed by ashing processes, the source/drain pattern part and an ohmic contact layer of the channel part are etched by dry etching processes. Accordingly, the active layer 14 of the channel part is exposed to separate the source electrode 8 and the drain electrode 10. Then, the photoresist pattern remaining in the source/drain pattern part is removed by stripping processes.
In FIG. 3C, the protection film 18 is formed on the gate insulation film 12 in which the source electrode 8, the drain electrode 10, the storage electrode 24, and the data line 4 are formed on the lower array substrate 1. The protection film 18 includes one of an inorganic insulation material, such as silicon oxide (SiOx) or silicon nitride (SiNx), or one of an acryl organic compound or organic insulation material, such as benzocyclobutene (BCB) and perfluorocyclobutane (PFCB). Then, the insulation film 18 is patterned by the photolithograpic and etching processes by using a third mask to form the drain contact hole 20 and the storage contact hole 26. The drain contact hole 20 extends through the protection film 18 and the drain electrode 10 to expose the ohmic contact layer 16, and the storage contact hole 26 extends through the protection film 18 and the storage electrode 24 to expose the ohmic contact layer 16.
In FIG. 3D, the pixel electrode 22 is formed on the protection film 18 by forming the transparent metal layer on the protection film 18 by the deposition method, such as sputtering. The transparent metal layer is made of Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), or Indium-Tin-Zinc-Oxide (ITZO). Then, the transparent metal layer is patterned by the photolithograpic and etching processes using a fourth mask to form the pixel electrode 22. Accordingly, the pixel electrode 22 contacts the drain electrode 10 through the drain contact hole 20 and contacts the storage electrode 24 through the storage contact hole 26.
Accordingly, in large-sized LCD devices, a capacitance (Cst) of the storage capacitor SC must be large in order to maintain a stable pixel voltage. However, since the storage capacitance is proportional to the capacitance (Cst) of the storage capacitor SC, an aperture ratio decreases. Accordingly, the capacitance (Cst) of the storage capacitor SC is increased by reducing a gap between the storage electrode 24 and the gate line 2.
However, the LCD device formed with the four masks limits increases of the capacitance (Cst) of the storage capacitor SC since the storage capacitor 24 and the first and second semiconductor layers 14 and 16 are simultaneously formed by the same pattern. For example, since the storage capacitor SC comprises the gate line 2, the gate insulation film 12, and the pixel electrode 22 and the first and second semiconductor layers 14 and 16, the gate insulation film 12 has a thickness of 4000 Å and a thickness of the first and second semiconductor layers 14 and 16 is 2000 Å. Accordingly, increasing of the capacitance (Cst) of the storage capacitor SC includes reducing the interval between the pixel electrode 22 and the gate line 2.
FIG. 4 is a cross sectional view of a storage capacitor of an LCD device according to the related art. In FIG. 4, a storage capacitor includes a gate line 2, a gate insulation film 12 and a protection film 18, and a pixel electrode 22. Accordingly, the gate insulation film 12 formed between the gate line 2 and the pixel electrode 22 has a thickness of 4000 Å and the protection film 18 has a thickness of 2000 Å of the thickness. Thus, since thicknesses of the gate line 2 and the pixel electrode 22 are limited, increasing the capacitance (Cst) of the storage capacitor is limited.